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Data Sheet
This discrete time accumulation or summation is equivalent to
integration in continuous time following the expression in
Equation 37:
ADE7854/ADE7858/ADE7868/ADE7878
Bit 2 (REHF) in the STATUS0 register is set when Bit 30 of
one of the xVARHR registers changes, signifying one of these
registers is half full. If the reactive power is positive, the var-hour
ReactiveEn ergy = ∫ q ( t ) dt = Lim ? ∑ q ( nT ) × T ?
? ∞ ?
T → 0 ? n = 0 ?
(37)
register becomes half full when it increments from 0x3FFF FFFF
to 0x4000 0000. If the reactive power is negative, the var-hour
register becomes half full when it decrements from 0xC000 0000
where:
n is the discrete time sample number.
T is the sample period.
On the ADE7858 / ADE7868 / ADE7878 , the total phase reactive
powers are accumulated in the AVARHR, BVARHR, and
CVARHR 32-bit signed registers. The fundamental phase reactive
powers are accumulated in the AFVARHR, BFVARHR, and
CFVARHR 32-bit signed registers. The reactive energy register
content can roll over to full-scale negative (0x80000000) and
continue increasing in value when the reactive power is positive.
Conversely, if the reactive power is negative, the energy register
underflows to full-scale positive (0x7FFFFFFF) and continues
to decrease in value.
to 0xBFFF FFFF. Analogously, Bit 3 (FREHF) in the STATUS0
register is set when Bit 30 of one of the xFVARHR registers
changes, signifying one of these registers is half full.
Setting Bits[3:2] in the MASK0 register enable the FREHF and
REHF interrupts, respectively. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the energy
registers, xVARHR (for REHF interrupt) or xFVARHR (for
FREHF interrupt), becomes half full. The status bit is cleared
and the IRQ0 pin is set to high by writing to the STATUS0
register with the corresponding bit set to 1.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
read-with-reset for all var-hour accumulation registers, that is,
the registers are reset to 0 after a read operation.
HPFDIS
[23:0]
DIGITAL
INTEGRATOR AIGAIN
IA
AVARGAIN
REVRPA BIT IN
STATUS0[31:0]
HPF
AVAROS
HPFDIS
TOTAL
AVARHR[31:0]
APHCAL
[23:0]
AVGAIN
REACTIVE
POWER
ACCUMULATOR
ALGORITHM
32-BIT
VA
HPF
DIGITAL SIGNAL PROCESSOR
VARTHR[47:0]
AVAR
2 4
Figure 71. Total Reactive Energy Accumulation
Rev. H | Page 55 of 100
REGISTER
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